The present invention relates to a nonvolatile semiconductor memory such as a flash type EEPROM, and more particularly to a nonvolatile semiconductor memory having an improved source line drive circuit capable of setting a potential of a source line to a fixed range regardless of a pattern of read data so as to prevent erroneous data from being read.
FIG. 1 shows a main part of the structure of a conventional nonvolatile semiconductor memory such as a flash type EEPROM. A surface of a memory chip 1 is occupied by a memory core section 2, and a peripheral circuit section other than the memory core section 2. The memory core section 2 comprises a memory cell array 3, a row decoder 4, and a bit line control circuit 5 including a sense amplifier 20 (FIG. 2) and a bit line charge circuit.
A row address signal is output from an address register 6 to be supplied to the row decoder 4 and a word line drive circuit 7. The row decoder 4 and the word line drive circuit 7 select a predetermined row of the memory cell array 3 based on a control signal from a command register 8, and apply a high potential to the selected predetermined row.
A column address signal is output to a column decoder 9 from the address register 6. The column decoder 9 selects a predetermined column of a memory cell array 3. Then, a bit line of the selected predetermined column and an I/O buffer 10 are connected to each other.
A well voltage control circuit 11 sets a voltage of a well where a memory cell is formed to a predetermined value based on the control signal from the command register 8. A source line drive circuit 12 sets a voltage VS of a source of the memory cell to a predetermined value based on the control signal from the command register 8.
FIG. 2 is an example of the structure of a conventional source line drive circuit.
The source line drive circuit 12 comprises an N channel MOS transistor 13. A control signal CR is applied to a gate of the MOS transistor 13. A source of the MOS transistor 13 is connected to a ground terminal GND (VSS). A drain source is connected to a source line 14.
The source line 14 is formed of metal such as aluminum. A wire resistor (including wire resistor of polysilicon wire used to intersect with a source line) 15 is provided between the MOS transistor 13 and the source line 14.
Memory cells 16 share one word line (control gate electrode) 18. Also, the memory cells 16 share one source diffusion layer 17. The source diffusion layer 17 is formed in a line manner in the row direction where the word line extends. Also, the source diffusion layer 17 contacts the source line 14 at a plurality of portions.
Drain diffusion layers of the memory cells 16 are connected to bit lines 19. The bit lines 19 are connected to sense amplifiers 20. Constant current sources 21 are connected between the bit lines 19 and power source terminals VDD, respectively to constitute the bit line control circuit 5.
In the above-explained nonvolatile semiconductor memory, an operation of each of data reading, writing, and is described in, for example, IEEE J. Solid-State Circuits, vol. 30, pp.1157-1164, November 1995.
The following will briefly explain the operation of data reading:
Specifically, the row address signal is decoded by the row decoder 4, a high potential (e.g. 5V) is applied to a predetermined word line 18. Also, the bit lines 19 are charged by the constant current sources 21.
In a state that data of the memory cells is "0", that is, an electron is stored in a floating electrode, a threshold value of each of the memory cells exceeds 5V. Due to this, even if the high potential is applied to the word line 18, each memory cell is not turned on.
As a result, each bit line 19 is maintained to be high potential (data "0"), and the high potential is guided to the I/O buffer 10 via the sense amplifier 20.
At the data reading operation time, almost all data is "1", almost all memory cells connected to the selected word line are turned on.
At this time, a large amount of current flows to the source line 14. As a result, the potential of the source line 14 rises due to the presence of the wire resistor 15 (including wire resistor of polysilicon wire).
Thus, if the potential of the source line 14 varies, the threshold voltages of the memory cells change. As a result, a read disturb characteristic is deteriorated. For example, FIG. 3 shows a state that the threshold voltage of a certain noticing memory cell is varied by data patterns of the other memory cells, which are connected to the same word line when the memory cells of 4096 bits (512 bytes per one word line) are connected to the word line.
If all data of the other memory cells is "0", no current flows. Due to this, the voltage of the source line connected to these memory cells does not rise, so that an apparent threshold voltage (Vt1) of the noticing memory cell is relatively low.
If all data of the other memory cells is "1", the current flowing to the source line 14 is increased in accordance with an increase in the number of data "1." As a result, the apparent threshold voltage of the noticing memory cell is increased by the rise of the voltage of the source line 14 and a body effect of the memory cell transistors. The value of the threshold voltage reaches the maximum (Vt2) when all memory cells other than the noticing memory cell are "1".
Thus, the threshold voltage of the noticing memory cell can be varied by "Vt2-Vt1=dVt" by the data patterns of the other memory cells. If the value of dVt is large, the following error will occur:
More specifically, data is erroneously regarded as "1" at the time of threshold voltage Vt1, or data is erroneously regarded as "0" at the time of the threshold voltage Vt2.
As a result, a reading defect will occur. Due to this, it has been necessary to take a larger value (margin) as data ("1", "0") threshold voltage level difference than the value of dVt, which is varied by the data patterns of the other memory cells, without being influenced by the value of dVt. However, to take such a large margin, the rise of the read voltage has been needed. As a result, the so-called read disturb characteristic has been worsened.